1. Field of the Invention
Method and apparatus to display a VLSI layout design, and in particular, a CAD/CAM method and apparatus that displays a VLSI design in photo-realistic detail and in real-time.
2. Background of the Related Art
Computer systems are most always used for the display of data in VLSI designs. The amount of data to display can vary from design to design, and the largest designs can contain hundreds of millions of separate pieces of information. Manipulation of the design database is part of the design and manufacturing of VLSI chips. At some point in the design, it is necessary to view the data in a graphical form on a display screen. A VLSI layout viewer and/or editor is used for this task.
A VLSI layout viewer reads received data descriptions of VLSI designs including sizes and locations of elements (e.g., polygons) on each of a plurality of layers in the design. The VLSI layout viewer generates images representing a view of the entire (or specific subset of selected layers) at various magnifications (scales), and draws the images on a display screen. Further, the VLSI layout viewer generates images representing various re-orderings of the layers (or a subset of the layers) of the VLSI design. For example, a specific layer can be brought to the front for viewing.
A VLSI layout editor is also a VLSI viewer, however the VLSI editor also allows for the modification of the data in the design. Both an editor and a viewer are generally used to display the VLSI data on a screen.
A first related art VLSI layout viewer displays for any viewpoint by iterating over all features visible for that viewpoint and simply drawing all the features to the display screen. At magnification (or zoom), this process can take minutes to draw an entire image. Additionally, since many of the features of the image are sub-pixel and/or fractional-pixel in dimension, the features appear incorrect, or xe2x80x9caliasedxe2x80x9d in the final image since the features will be drawn on pixel boundaries.
A second related art technique modifies the first to speed the drawing process by choosing not draw anything in certain areas of the design. Instead of drawing the details of all of the features, a solid box is drawn that represents that entire area. Drawing one solid box is much faster than drawing each smaller feature. However, the image quality is decreased, and the image is inaccurate and does not resemble a photo-realistic image.
A third related art technique simply draws less, for example, instead of drawing millions of features, only a fraction of the features are drawn. The criteria used by the third related art technique as to whether a selected feature is drawn is determined by randomly selecting every Nth feature (e.g., N=10). The assumption is that random selection is as good as any other criteria. The drawing speed is increased, but it does not increase by a factor of N since each polygon still needs to be tested randomly for display.
A fourth related art technique to speed up the VLSI drawing process is to only draw features that will appear on the screen as a certain size or larger. The fourth related art technique works no matter the size of the VLSI design because all the features will continue to scale down. As a drawing editor zooms out to higher scales, all features get smaller. A threshold is set and features that will appear less than N pixels on the screen are not drawn. For example, N is set to 1, then any feature less than 1 pixel on a side will be discarded. This method of culling speeds up the drawing process, but generates inaccuracies in the image.
A fifth related art technique is to determine which features are not visible at all and then, those features are not drawn. Features correspond to different layers of a VLSI layout and can be viewed in different stacking orders. That is, one layer may appear (on the display) as xe2x80x9cabovexe2x80x9d or xe2x80x9cbelowxe2x80x9d another VLSI design layer. If one layer is going to appear above another layer, then the underneath layer is not drawn because it is occluded by the xe2x80x9cabovexe2x80x9d layer upon display when the entire VLSI image is drawn.
A sixth related art technique is to draw everything but allow the user to halt the drawing process while the drawing is still ongoing. Thus, an arbitrarily long redraw process can at least be stopped by a user at any time. The related art VLSI layout editors use this technique to specifically address the problem of slow redraw times.
A seventh related art technique is to convert a VLSI design into an image and to view the image of the design. However, the size of the image file created when the design is converted to an image could be terabytes, and consequently, the available techniques to view it as an image are limited. One related art option is a clipmap image disclosed in U.S. Pat. No. 5,760,783. However, using a clipmap or any other pure image viewing solution disadvantageously generates a transformation cost (both in terms of computation time and memory cost), and the inability to change the image quickly and easily once the transformation has been done.
As described above, the related art VLSI layout viewers have various disadvantages. The related art VLSI layout viewers have slow display and re-draw times for VLSI designs. Further, such problems will get worse as the number of polygons in modern VLSI layouts reach into to the tens or hundreds of millions and displaying each of those polygons at once can take terabytes of data. In addition, inaccuracies occur in the display of the designs in an attempt to increase display speed. When viewed at low magnification, most of the polygons can be smaller than a single pixel in one or both dimensions, and drawing the polygons without proper filtering produces noticeable aliasing artifacts.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a layout viewer and method of using same that uses a pre-computed image that represents some portion of the VLSI design.
Another object of the present invention is to provide a layout viewer and method of using same that uses previously drawn portions of a VLSI design in a currently drawn VLSI design.
Another object of the present invention is to provide a layout viewer and method of using same that provides real-time navigation of a VLSI layout independent of the size of the design.
Another object of the present invention is to provide a layout viewer and method of using same that provides an accurate photo-realistic representation of the VLSI layout on a display screen.
Another object of the present invention is to provide a layout viewer and method of using same that displays a VLSI layout without aliasing artifacts.
Another object of the present invention is to provide a layout viewer and method of using same that provides a representation of the VLSI layout independent of a size of the VLSI layout.
Another object of the present invention is to provide a layout viewer and method of using same that uses a direct rendering of polygons and drawing of texture data to display images of a VLSI layout.
Another object of the present invention is to provide a layout viewer and method of using same that uses different methods of display for a VLSI design depending on the level of magnification.
Another object of the present invention is to provide a layout viewer and method of using same that provides accurate real-time navigation of a displayed representation of a canonically expressed VLSI design independent of the size of the displayed image representation using a bounded representation of the canonical expression for display.
Another object of the present invention is to provide a layout viewer and method of using same that eliminates long redraw problems and incorrect depictions when rendering a representation on a display screen of a canonically expressed VLSI layout.
Another object of the present invention is to provide a layout viewer and method of using same that determines and pre-computes displayable representations of sub-designs of the VLSI design for a subset of the possible displayable magnifications.
Another object of the present invention is to provide a layout viewer and method of using the same that renders the data from a VLSI layout in either an opaque or semi-transparent style.
Another object of the present invention is to provide a VLSI layout viewer and method of using the same that draws VLSI data opaquely so that data stacked xe2x80x9cabovexe2x80x9d occludes data stacked xe2x80x9cbelowxe2x80x9d.
Another object of the present invention is to provide a VLSI layout viewer and method of using the same that draws VLSI data semi-transparently so that data will be drawn with an opacity that allows data stacked xe2x80x9cbelowxe2x80x9d to be visible relative to data stacked xe2x80x9cabove.xe2x80x9d
Another object of the present invention is to provide a VLSI layout viewer and method of using the same that draws VLSI data semi-transparently so that data drawn with nothing xe2x80x9cunderneathxe2x80x9d appears opaque.
To achieve at least these objects and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a VLSI layout editor that includes a first memory that stores a canonical expression of a VLSI layout having a plurality of layers and a display controller coupled to the first memory that generates a displayable representation of ordered layers of the VLSI layout that tracks changes in a user viewpoint, wherein the displayable representation includes a precomputed image that represents a portion of the VLSI layout, and wherein the precomputed image is used in two or more user viewpoints.
To further achieve at least these objects and other advantages in whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a method of viewing a VLSI layout design that includes loading a VLSI layout design into a first memory, determining a number of LODs from a base representation level to a top level of a chip pyramid according to the first representation, determining a first transition threshold and second transition threshold at a higher LOD from the first transition threshold that subdivide the chip pyramid into three sections, and displaying a representation of the VLSI layout design using a first displaying technique below the first transition threshold, a second displaying technique between the two transition thresholds and a third displaying technique above the second transition.
To further achieve at least these objects and other advantages in whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a method of rendering a viewable representation of an integrated circuit (IC) layout that includes loading a canonical form of the IC layout into a first memory, determining a chip pyramid structure having a plurality of levels of detail (LOD) from a base LOD to a top LOD according to the canonical form of the IC layout, determining hierarchy data for selected sub-designs in the canonical form and storing the hierarchy data in a second memory, determining a selected LOD in the chip pyramid to display the IC layout according to an input viewpoint, displaying the IC layout using stored sub-images of selected portions of the canonical form when the selected LOD is above a first threshold, and displaying the IC layout by using the canonical form to directly display polygons when the selected LOD is below the first threshold.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.